Description: 许多现代浮点单元的一项主要体系结构功能，是能够将一个乘法与后面紧跟的加法作为单个运算执 行，且没有中间舍入误差。例如，Intel 的 Itanium 体系结构提供了一些指令，将三元运算 (a*b+c) 、(a*b-c) 和 (c-a*b) 中的每一个都组合为单个浮点指令（分别为 fma、fms 和 fnma）。这些单个 指令都比执行独立的乘法和加法指令快，并且因为没有中间乘法舍入，所以更为精确。该优化可以显 著提高那些含有多个交错乘法和加法运算的函数的速度-many modern floating point unit of a major system structure and function is to be a follow closely behind multiplication and addition of implementation as a single operator, with no intermediate rounding error. For example, Intel's Itanium architecture provides a number of directives to the ternary operator (a * b, c), (a * b-c) and (c-a * b) each have a portfolio to a single floating point instructions (Fullmetal respectively, and fms fnma) . These individual instruction than the implementation of an independent and additive multiplication instructions quickly, and because no middle multiplication into homes, so more precise. The optimization can significantly increase those containing more than staggered multiplication and addition operations function of the speed Platform: |
Size: 6440 |
Author:jack |
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Description: 各种51单片机源程序集，包括浮点数的计算，多字节的加减等算法的实现-SCM source scripts, including floating point calculations, multi-byte such as addition and subtraction algorithm implementation Platform: |
Size: 125981 |
Author:周云 |
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Description: 许多现代浮点单元的一项主要体系结构功能，是能够将一个乘法与后面紧跟的加法作为单个运算执 行，且没有中间舍入误差。例如，Intel 的 Itanium 体系结构提供了一些指令，将三元运算 (a*b+c) 、(a*b-c) 和 (c-a*b) 中的每一个都组合为单个浮点指令（分别为 fma、fms 和 fnma）。这些单个 指令都比执行独立的乘法和加法指令快，并且因为没有中间乘法舍入，所以更为精确。该优化可以显 著提高那些含有多个交错乘法和加法运算的函数的速度-many modern floating point unit of a major system structure and function is to be a follow closely behind multiplication and addition of implementation as a single operator, with no intermediate rounding error. For example, Intel's Itanium architecture provides a number of directives to the ternary operator (a* b, c), (a* b-c) and (c-a* b) each have a portfolio to a single floating point instructions (Fullmetal respectively, and fms fnma) . These individual instruction than the implementation of an independent and additive multiplication instructions quickly, and because no middle multiplication into homes, so more precise. The optimization can significantly increase those containing more than staggered multiplication and addition operations function of the speed Platform: |
Size: 6144 |
Author:jack |
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Description: 由于Java的简单类型不能够精确的对浮点数进行运算，这个工具类提供精确的浮点数运算，包括加减乘除和四舍五入。-Because of Java s simple types can not be accurately carried out on the floating-point computing, the tools provide accurate floating-point, including addition and subtraction multiplication and division and rounding. Platform: |
Size: 1024 |
Author:张齐 |
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Description: 哈工大 计算机学院 组成原理大作业
运用程序模拟浮点数的运算
1. 用户输入十进制的阶码和尾数
2. 根据浮点运算的法则进行运算。
3. 浮点四则运算：加减法可以使用同一种对阶方法，乘除法可以使用同一种对阶方
4. 对运算的方法得到的结果进行检查，看是否溢出，并把结果规格化。-HIT computer college composed of the principle of operation the use of large floating point computing simulation 1. The order of user input decimal code and mantissa 2. In accordance with the rules for floating point calculations. 3. 4 floating-point operations: addition and subtraction can use the same type of order method, multiplication and division can use the same side of the band 4. The method of computing the results of the inspection to see if overflow, and the results normalized. Platform: |
Size: 11264 |
Author: |
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Description: vim7.2最新源码。Vim 7.2修正了大量bug并更新了运行时文件，最主要的新特性在于加入对脚本浮点数的支持。另外，修正了上一版中发现多个导致崩溃和威胁安全的问题。-vim7.2 the latest source. Vim 7.2 a large number of bug fixes and updated runtime files, the most important new features to add to the script floating point support. In addition, the amended version of one found on a number of lead to the collapse and the threat of security. Platform: |
Size: 8981504 |
Author: |
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Description: 在128*128的网格上求解2维波动方程来模拟大范围的水波。用一个像素渲染程序完成对波动方程的时间积分，结果存放于一个浮点数纹理中，.然后将此纹理传给渲染模块。此外使用凹凸贴图来描述水面的细节波纹，这会给稍后的逐像素渲染带来逼真的水面闪烁高光效果.-128* 128 grid on the solution of 2-dimensional wave equation to simulate a wide range of water. With a pixel shader program to complete the wave equation of time points, the result is stored in a floating point texture,. And then this texture to the rendering module. In addition the use of bump mapping to describe the details of the surface corrugation, which will later bring about-by-pixel rendering realistic water effects of high light flashes. Platform: |
Size: 1740800 |
Author:ding |
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Description: 通过4X4独立按键输入两个浮点数，并在LCD1602上进行显示，此单片机系统可精确计算两个浮点数的加减乘除，保留小数点后3位数字 -By 4X4 independent button to enter two floating-point numbers, the LCD1602 display, microcontroller system can accurately calculate the two floating-point addition and subtraction, multiplication and division, three digits after the decimal places Platform: |
Size: 84992 |
Author:王鹏 |
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Description: 除必要循环外，只使用位操作来模拟CPU的算术运算，可实现整数及浮点的加减乘除-In addition to the necessary circulation only use bit manipulation to simulate the CPU arithmetic, integer and floating-point addition, subtraction, multiplication, and division Platform: |
Size: 4096 |
Author:宋麒 |
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Description: 该源码利用Verilog HDL语言成功实现了浮点数的加法运算，包括全部工程以及Verilog 源码，经验证，该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful implementation of the program the floating point adder. Platform: |
Size: 12144640 |
Author:zhu yue |
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Description: 使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。-Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision Platform: |
Size: 5120 |
Author:周和 |
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Description: 实现了基于FPGA的FFT变换，从最基本的32位2进制浮点数加减乘运算模块开始，组装出FFT模块。同时仿真文件中有32位浮点数转换为实数的仿真模块便于调试-Realized FPGA-based FFT transform, starting with the most basic 32-bit binary floating-point addition and subtraction multiplication module, a FFT module assembly. At the same time simulation files in 32-bit floating-point number is converted to a real number of simulation modules for debugging Platform: |
Size: 3136512 |
Author:韦壮焜 |
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Description: 32位浮点数加法，使用的语言是verilog。其中包括的是工程中的v文件。-32-bit floating-point addition, the use of language is verilog. Including is v of the engineering documents.
Platform: |
Size: 2048 |
Author:小王 |
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Description: 《基于FPGA的单精度浮点数乘法器设计》详细介绍了按照IEEE754标准在FPGA上实现单精度浮点加减乘除的方法(The design of single precision floating point multiplier based on FPGA introduces in detail the way of realizing single precision floating point addition, subtraction and multiplication and division based on IEEE754 standard on FPGA.) Platform: |
Size: 2432000 |
Author:sisuozheweilai |
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